1. Field of the Invention
The present invention relates to a liquid crystal display and more particularly relates to a liquid crystal driver capable of enlarging and displaying a low resolution image signal on a liquid crystal panel.
2. Description of Related Art
A description of a related liquid crystal display will be given using FIG. 2 to FIG. 5.
FIG. 2 is a block diagram of a related liquid crystal driver. FIG. 3 is a timing chart showing the operation of a related liquid crystal driver. FIG. 4A and FIG. 4B are block diagrams of liquid crystal displays employing related liquid crystal drivers.
In FIG. 2, numeral 101 indicates a data bus for transmitting display data. Numeral 102 indicates a clock CL2 synchronized with the display data of the display data bus 101. Further, numeral 103 indicates a display data capture start signal El, numeral 104 indicates a horizontal synchronization signal CL1 generated every horizontal period and numeral 105 indicates a reference gradation voltage that is a reference for a gradation voltage outputted by this liquid crystal driver. Moreover, numeral 201 indicates a shift register, numeral 202 indicates a latch signal group generated by the shift register 201, numeral 203 indicates a data latch, numeral 204 indicates a data bus for transmitting line data outputted by the data latch 203, numeral 205 indicates a line data latch for simultaneously capturing line data transmitted by the data bus 204, numeral 206 indicates a data bus for transmitting line data outputted by the line data latch 205, numeral 207 indicates a gradation voltage generator for generating a gradation voltage from the data bus 206 and the reference gradation voltage 105 and numeral 208 indicates a signal line group (hereinafter referred to as a "drain line group") for transmitting the gradation voltage generated by the gradation voltage generator 207.
In FIG. 4A and FIG. 4B, numeral 401 indicates a data bus for transmitting display data supplied from a system (not shown in the drawings) and a synchronization signal. Numeral 402 indicates a controller for generating display data and timing signals etc. for liquid crystal driving use based on display data and synchronization signals transmitted via the data bus 401. Further, numeral 403 indicates a liquid crystal driver, numeral 404 and 404' indicate scanning drivers, numeral 405 indicates a power supply and numeral 406 and 406' indicate liquid crystal panels. Moreover, numeral 407 indicates a data bus for transmitting liquid crystal display data and timing signals supplied to the liquid crystal driver 403 from the controller 402, numeral 408 indicates a data bus for transmitting signals for controlling the scanning driver 404 and numeral 409 indicates a signal line for transmitting an alternating signal supplied to the power supply 405. Numeral 410 indicates a signal line group (hereinafter referred to as a "drain line group") for transmitting gradation voltages generated by the liquid crystal driver 403. Numeral 411 indicates a signal line group (hereinafter referred to as a "gate line group") for transmitting line select/deselect voltages generated by the scanning driver 404. Numeral 412 indicates a, power supply line for transmitting a reference voltage for the line select/de-select voltage generated by the power supply 405 to the scanning driver 404. Numeral 413 indicates a power supply line for transmitting a voltage that is a reference for the gradation voltages generated by the liquid crystal driver 403. Numeral 414 indicates a power supply line for providing a voltage to opposing electrodes of the liquid crystal panel 406. Numeral 418 indicates supplementary capacitors provided in order to prevent voltage leakage from the liquid crystal 417. Numeral 415 indicates a power supply line for supplying a voltage to the supplementary capacitors 418 of the liquid crystal panel 406. Numeral 416 indicates a "Thin Film Transistor" (hereinafter abbreviated to "TFT") for carrying out a switching operation. Numeral 417 indicates a liquid crystal which is described as a condenser.
The details of the liquid crystal display of FIG. 4A are described based on FIG. 2 and FIG. 3. Here, a description is given with a 640 pixel portion of valid display data being transmitted to the liquid crystal driver.
When the display data capture start signal 103 is valid, the shift register 201 sequentially puts the latch signal group 202 to valid (refer to FIG. 3) in accordance with the clock 102 synchronized with the display data to be transmitted by the display data bus 101.
The data latch 203 then captures the display data by sequentially latching the display data transmitted via the display data bus 101 in accordance with the latch signal group 202. The display data stored at the data latch 203 also appears at the data bus 204 as shown in FIG. 3 because the latch signal group 202 is generated in synchronization with the display data transmitted via the display data bus 101.
When the horizontal synchronization signal 104 becomes valid, the line data latch 205 simultaneously captures the display data stored at the data latch 203 via the data bus 204. The line data latch 205 then transmits this captured display data to the gradation voltage generator 207 via the data bus 206. The gradation voltage generator 207 then generates gradation voltages in response to this display data and outputs the gradation voltage via the drain line group 208 (410).
When one horizontal line portion of display data is stored at the line data latch 205, the shift register 201 and the data latch 203 start the operation to catch display data for the next line. The above operation is then sequentially repeated during displaying.
The conditions for the liquid crystal driver of this related example to carry out displaying will be described together with a further driving circuit using FIG. 4A.
In FIG. 4A, the controller 402 converts the display data and synchronization signal transmitted from the system bus 401 into display data for liquid crystal driver use and each of the various timing signals and supplies this data and the various signals to the appropriate parts. The liquid crystal driver 403 then captures the display data in sequence and generates and outputs a gradation voltage corresponding to display data for one horizontal line portion. The liquid crystal driver 403 has already been described using FIG. 2 and FIG. 3.
The scanning driver 404 applies a select voltage or de-select voltage to the gate line group 411 in synchronization with the output of the gradation voltage, i.e. the scanning driver 404 applies a select voltage to the gate line connected to the first line while the liquid crystal driver 403 outputs a gradation voltage corresponding to the display data of the first line, with a de-select voltage being applied to gate lines of the remaining lines. TFTs 416 of pixel parts for the first line then become selected and a gradation voltage transmitted via a signal line of the drain line group 410 is applied to liquid crystals 417 and supplementary capacitors 418 of pixels of the first line.
Next, a select voltage is applied to the gate line connected to the second line when the liquid crystal driver 403 outputs a gradation voltage corresponding to display data for a second line. The gradation voltage is therefore applied to the TFTs of the pixels for the second line in the same way as for the first line. A de-select voltage is then applied to the gate lines of the first line and the remaining lines. The TFT 416 of the first line therefore goes off and the load (i.e. the applied gradation voltages) accumulated at the liquid crystal 417 and supplementary capacitors 418 for each of the pixel parts is stored.
Gradation voltages corresponding to display data for one picture portion can then be applied to all of the pixel parts by repeating the above operation while sequentially changing the line to which a select voltage is applied.
The operation of the related liquid crystal display shown in FIG. 4B is also basically the same as the liquid crystal display of FIG. 4A. However, with the liquid crystal panel 406' utilized in the liquid crystal display of FIG. 4B, the supplementary capacitors 417 of the pixel parts put on by the TFT 416 are connected to a separate neighboring gate line and a selection voltage therefore cannot be applied simultaneously to two neighboring gate lines.
With related liquid crystal displays, however, the picture becomes unsightly when the resolution of inputted valid display data and the resolution of the liquid crystal panel do not coincide. This problem is described in detail using FIG. 5.
In the example shown in FIG. 5, valid display data of 640 horizontal pixels and 480 vertical lines is shown on a liquid crystal display having 1024 horizontal pixels and 768 vertical lines.
As only a 640 pixel portion of display data is transmitted in the horizontal direction, the shift register 201 (refer to FIG. 2) of the liquid crystal driver 403 only puts a 640 pixel portion of the latch signal group 202 as being valid. Portions corresponding to latch signal groups 202 thereafter for the data latch 203, line data latch 205 and gradation voltage generator 207 are therefore not inputted as valid display data. Displaying is therefore not possible for regions for which this latch signal is not valid.
Further, only a 480 line portion of display data is transmitted in the vertical direction. Display data for the following frame therefore gets transmitted during the operation of selecting the gate lines of the lower part of the displayed picture. The image to be displayed at the upper part of the picture in the next frame therefore gets displayed at the lower part of the picture for the current frame, causing a problem.